An integrated circuit (“IC”) is a device (e.g., semiconductor device) that includes many electronic components. An electronic component can be transistor, resistors, diodes, etc. . . . Furthermore, these electronic components can be interconnected together (by using wiring) to form multiple circuit components, such as gates, cells, memory units, etc. . . .
The process of producing these circuit components and/or wiring (e.g., by using an etching process) on an IC often results in circuit components and/or wiring that have different heights for the same layer of the IC. Because an IC typically has several layers that are stacked one on top of each other, it is desirable to have circuit components and/or wiring to have the same height along the entire layer of the IC (i.e., to have a flat surface along the entire layer). This ensures that subsequently placed layers of the IC remain parallel to the other layers of the IC.
To produce a layer of an IC with a flat surface (e.g., global planarization of the layer), a chemical mechanical polishing (“CMP”) process is performed after the circuit components and/or wiring are produced on a layer of the IC. As the name implies, a CMP process is a procedure that polishes the layers of the IC to flatten the surface of the layer of the IC. Typically, the CMP process uses an abrasive and/or corrosive slurry that removes excess topological features (e.g., circuit components that extend beyond a certain height above the surface of a particular layer) of the layers of the IC.
However, CMP is a density sensitive process. In particular, the CMP requires that the density of the layer of the IC be within a minimum and maximum range. In other words, for the CMP process to be effective, the density of the IC layer has to be within a particular density range. Ideally, the density of the layer should be uniform throughout the entire layer. The density of the IC layer can be defined as the total area of the circuit components and wiring divided by the total area of the IC layer. When the density of the layer is not uniform or is not within the particular range, some of the side effects of the CMP process may include removing essential topological features (e.g., circuit elements) of the IC layer.
To resolve this issue, engineers insert fills in certain regions of the IC layer to create uniform density throughout the entire IC layer and/or to ensure that local regions of the IC layers meet the minimum density values for the CMP process. These fills are inactive and non-functional materials that are inserted between wiring and circuit components. FIGS. 1 and 2 conceptually illustrate a portion of a Manhattan layout before and after fills are inserted. As shown in FIG. 2, these square fills have one size and are inserted between interconnects.
Current methods of inserting fills are designed for Manhattan IC layouts. Furthermore, current methods of inserting fills do not produce optimal fill configurations. Therefore, there is a need in the art for a method of optimally inserting fills in an IC layout. Ideally, such a method can optimally insert fills in non-Manhattan layouts.